MT48LC16M16A2P-75IT

MT48LC16M16A2P-75IT, Micron Technology, TSOP, memory, 3 3.6 V, –5 –5 μA

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PartNumber:: MT48LC16M16A2P-75IT

Brand:: Micron Technology - MT | Pack: TSOP | D/C: 11+

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Products Upload time: 2012-09-19

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Part Number:MT48LC16M16A2P-75IT
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Product Summary

The MT48LC16M16A2P-75IT is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x4s 67,108,864-bit banks is organized as 8192 rows by 2048 columns by 4 bits. Each of the x8s 67,108,864-bit banks is organized as 8192 rows by 1024 columns by 8 bits. Each of the x16s 67,108,864-bit banks is organized as 8192 rows by 512 columns by 16 bits.

Parametrics

MT48LC16M16A2P-75IT absolute maximum ratings: (1)Supply voltage VDD, VDDQ: 3 3.6 V; (2)Input high voltage: Logic 1; All inputs: VIH 2 VDD + 0.3 V 4; (3)Input low voltage: Logic 0; All inputs: VIL –0.3 +0.8 V 4; (4)Output high voltage: IOUT = –4mA: VOH 2.4 – V; (5)Output low voltage: IOUT = 4mA: VOL – 0.4 V; (6)Input leakage current:–5 5 μA; (7)Output leakage current: –5 –5 μA.

Features

MT48LC16M16A2P-75IT features: (1)PC100- and PC133-compliant; (2)Fully synchronous; all signals registered on positive; (3)edge of system clock; (4)Internal, pipelined operation; column address can be changed every clock cycle; (5)Internal banks for hiding row access/precharge; (6)Programmable burst lengths: 1, 2, 4, 8, or full page; (7)Auto precharge, includes concurrent auto precharge and auto refresh modes; (8)Self refresh mode (not available on AT devices); (9)Auto refresh; (10)64ms, 8192-cycle (commercial and industrial); (11)16ms, 8192-cycle (automotive); (12)LVTTL-compatible inputs and outputs; (13)Single +3.3V power supply.